Intel’s graphics head Raja Koduri teased the new Xe dGPUs that is presently being tested at the company’s Folsom labs. The tweets by the graphics head showed off three GPUs, one of which was named as the Big Fabulous Package (BFP). This is a prototype cooling system and the test platform. The BFP is a 4-tile Xe dGPU that is aimed at HPC workloads.
BFP – big ‘fabulous’ package😀
— Raja Koduri (@Rajaontheedge) June 25, 2020
Earlier in 2020, Intel showed the first references to a 500 W Arctic Sound GPU coupled to HBM2e memory and with PCIe Gen4 compatibility. Now, the graphics head is giving people a glimpse of what appears to be a family of Xe GPUs from Intel’s Folsom Labs. The set includes the 4-tile Arctic Sound, Xe DG1, and a Xe HPC accelerator.
Intel’s graphic head Raja Koduri teases Xe dGPU from Folsom Labs. (Image: Raja Koduri; Twitter)
Raja teased the three GPUs and test setup. One of them was already an earlier revealed Xe part for HPC. The new ones flashed are expected to be the Xe DG1 and a 4-tile Arctic Sound prototype. Intel dGPUs are expected to have multi-chip modules stacked in 1, 2, and 4 tile-based configurations. The graphics head in the tweet refers to the 4-tile Arctic Sound GPU as the Big Fabulous Package (BFP). The “BFP” prototype has a 48 V power requirement. BFP is, therefore, targeted at servers and HPC workloads and, not meant for gaming purposes.
However, there is still time before people get to see the proper Xe mainstream dGPU. Raja Koduri earlier confirmed that the primary focus of Intel is on enhancing integrated graphics and “segments immediately above“. Accordingly, people will also see first the Xe going mainstream in Tiger Lake’s Gen12 iGPUs. Though Tiger Lake may not beat the AMD Ryzen 4000 Renoir APUs in terms of enhanced CPU power, the integrated Gen12 Xe can give Renoir’s Vega 8 a run for its money.
Based on what Intel has talked about the Ponte Vecchio chip, it looks more like Intel in all is onboard the MCM train with each chip consisting of several Xe GPU tiles that will be interconnected to create a monster of a GPU.
Intel’s Big Fabulous Package teased on chief Raja Koduri’s twitter page. (Image: Raja Koduri; Twitter)
The GPU architecture by Intel uses a tile-based design, though slices are also used. Among other components in the GPU, each tile has a set number of “sub-tiles” that packs eight execution units each. Like, the 11th-generation GT2 has one tile comprising of eight sub-tiles at eight EUs each. Intel’s GT1.5 design totals 48 EUs while the low-end GT1 has 32 EUs. The biggest count by Intel is the ninth-generation GT3 with two tiles comprising of 96 EUs each. Translated into core counts, the 9th Gen GT3 consists of 768 cores, and the 11th Gen GT2 has 512 core. The newer change is the four-tile design in Gen12.
In March 2019, Intel launched its Graphics Command Center. The center works with Intel’s onboard graphics solutions and also includes options for launching games, game optimization, and the chance to tweak global GPU options across various applications. The center offers the necessary functionality for onboard Intel GPU users, though the foundation was laid for a more comprehensive Intel GPU software suite. Along with hardware development, Intel is investing a lot into driver development with cumbersome optimization processes.
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